1. Field of the Invention
The present invention relates to the field of programming and testing integrated circuits or systems.
2. Art Background
Various techniques have been developed to enable programming and testing of programmable elements (memory locations) of a programmable logic device (PLD) or complex programmable logic device (CPLD). Generally, programmable elements within CPLDs have been programmed by applying program data through a parallel interface of the CPLD. When a CPLD is programmed through a parallel interface, the data used for programming a memory location is provided on several device pins, and the data that is output during the verification of a memory location is also provided on several device pins. These device pins may or may not comprise the same device pins.
A typical flow diagram for programming every memory location with a desired pattern in a CPLD is illustrated in FIG. 1. The programming flow chart illustrated in FIG. 1 may be used, for example, in programming a CY7C371 CPLD manufactured by Cypress Semiconductor Corporation. At step 100, a power supply voltage is applied to the CPLD. Typically, the power supply voltage applied to the CPLD comprises +5.0 volts or +3.3 volts. At step 102, a programming voltage is applied to the CPLD. The programming voltage is typically an elevated voltage which is used to program the memory locations in the CPLD. A typical programming voltage comprises +12.0 volts. At step 104, the silicon identification for the particular CPLD under test is read from a memory location within the CPLD. The silicon identification is verified to match the CPLD device under test (e.g. CY7C371). At step 106, a program cycle counter is read and verified. The program cycle counter indicates the number of times the CPLD has been programmed. For quality and reliability purposes, at step 108, the program cycle counter is checked to determine if it contains a value greater than or equal to a predetermined number of programming attempts (e.g. 100 programming attempts). If the program cycle counter is greater than or equal to the predetermined number of programming attempts, the device is discarded at step 110. If the device has been programmed less than the predetermined number of times, program data is applied to the parallel interface of the CPLD and every memory location is programmed with a background pattern at step 112. Background programming ensures that every programmable memory location contained within the device is programmed, including main array bits, configuration bits, user identification bits, program cycle counter bits and a security bit. Every programmable element is programmed regardless of whether its present state is programmed or unprogrammed. This is done to provide for a consistent erasure of all of the memory locations. At step 114, all of the memory locations are erased. At step 116, the erasure of the memory locations is confirmed. Step 116 is referred to as the blank verify.
At step 118, a desired program pattern is programmed into the CPLD. FIG. 2 illustrates a general program flow chart for programming the desired pattern into the CPLD, and will be described in detail below. At step 120, the configuration bits of the CPLD are programmed again to boost or raise the overall margin. Configuration bits in a CPLD may comprise programmable locations that control the configuration of macrocells, a programmable interconnect matrix (PIM), or a product term matrix (PTM). At step 122, the program cycle counter is updated and verified. At step 124, all of the memory locations are read at power supply rails to verify that no disturb problems exist in the programming of the CPLD. Disturb problems cause unintentional programming of a memory location while programming another related location, such as a location on the same row or column. At step 126, a security bit of the CPLD is optionally programmed and verified. At step 128, the programming voltage is removed from the CPLD, that is, the programming voltage is forced to a non-programming voltage (e.g. ground). At step 130, the power supply voltage is removed from the CPLD and the programming flow stops.
FIG. 2 illustrates one example of parallel programming a desired pattern into a CPLD according to step 118 of FIG. 1. The programming flow starts at step 202. At step 204, a row address is loaded into a row address register. The row address indicates the row address of the memory location to be programmed. At step 206, a column address is loaded into a column address register. The column address indicates the column address of the memory location to be programmed. At step 208, program data is placed onto parallel interface data input pins. At step 210, a counter variable C is set to zero. The counter variable C indicates the number of attempts at programming a particular memory location. At step 212, the program flow checks to see if the counter variable has reached the maximum number of programming attempts allowed. In one example, C may comprise a maximum of four programming attempts. If C has reached the maximum number of programming attempts, the programming of the CPLD fails as indicated by step 214. If C has not reached the maximum number of programming attempts, the program flow programs data into a memory location at step 216. At step 218, C is incremented by one.
At step 220, programming of the memory location is immediately verified to determine if another attempt to program the same memory location is required. If the data read from the programmable memory location (verify data) does not match the program data, the program flow returns to step 212 and attempts to reprogram the memory location if C has not reached the maximum number of programming attempts. If the verify data matches the program data at step 220, the program data is programmed again into the memory location at step 222. The reprogramming of the program data at step 222 is termed "overprogramming." Overprogramming boosts the charge stored at a programmed memory location. At step 224, the program flow determines if the last column address of the programmable memory locations has been programmed. If it has not, the column address is updated and the program flow returns to step 206. If the last column address has been reached, the program flow determines if the last row address has been reached at step 226. If it has not, the row address is updated and the program flow returns to step 204. If the last row address has been reached, the program flow stops at step 228.
Parallel programming and verification of programming are not always possible or efficient. For example, when a CPLD has been affixed to a printed circuit board (PCB), it is expensive, time consuming, and often impractical to test an individual component by a parallel programming technique. Additionally, programming a device using a parallel programming interface requires the control of a significant number of pins. In many cases, as many as 25 to 30 pins must be controlled in a parallel programming interface. As a result, various techniques have been developed to enable testing of a CPLD using test logic having a serial programming interface. Program data to be provided to programmable memory locations of a CPLD are input through a serial input port. Verification data read from the programmable memory locations is read from a serial output port. The serial programming interface provides a more efficient interface for programming a device already soldered onto a PCB.
One type of serial programming interface is incorporated into the 22V10D Flash PLD designed by Cypress Semiconductor Corporation. The 22V10D includes a test circuit coupled to memory locations as generally illustrated in block diagram form in FIG. 3a. FIG. 3a shows a 22V10D Flash PLD 300 which includes programmable memory 304 coupled to parallel input data at node 318 and parallel output data at node 332. The 22V10D 300 incorporates a serial interface test circuit 303 which is not compatible with the IEEE 1149.1 (JTAG) specification described below, but is able to generally implement a serial program flow consistent with FIG. 1 and FIG. 2. Test circuit 303 comprises control logic 306 which controls the programming of memory 304. Control logic 306 receives control signals from the parallel data input, including a programming voltage at node 320, register select signals RSEL0 at node 322 and RSEL1 at node 324 which are used to select one of four shift registers, and a program pulse DO.sub.-- IT at node 326. Additionally, control logic 306 receives a serial input clock SCLK at node 328. Test circuit 303 also includes four shift registers, namely: data shift register 310, column address shift register 312, row address shift register 314 and mode select shift register 316. The four shift registers receive serial input data from SDI at node 330 and the serial input clock SCLK at node 328.
With reference to FIG. 2, a row address for a memory location to be programmed in the 22V10D is serially shifted into row address shift register 314 at step 204, a column address is serially shifted into column address shift register 312 at step 206 and program data is serially shifted into data shift register 310 at step 208. The 22V10D must use the externally supplied register select signals RSEL0 and RSEL1 to determine which register is selected at a given time. In response to a program instruction loaded into mode select shift register 316, program data is programmed into a memory location at step 216 when a program pulse is applied on DO.sub.-- IT at node 326. As a result of the programming step, the programmed data is immediately fast verified. Verify data is not loaded into the data shift register and then shifted out of the 22V10D to be compared against the program data. Instead, an internal comparison of the verify data and the program data is made by compare logic 308. The result of that comparison is output on one of the parallel data output pins at a predetermined amount of time following a program pulse on DO.sub.-- IT at node 326. The result of the comparison is combinatorial in nature, that is, the result is not registered nor output on one of the parallel data outputs in response to a clock signal. As a result, one 22V10D cannot be cascaded with another 22V10D and continue to support the verify method described above.
The comparison of the verify data read from the memory location and the program data stored in the data shift register is accomplished by compare logic 308. Compare logic 308 is further illustrated in FIG. 3b, which shows exclusive OR (XOR) gate 380 comparing the data shift register bit zero (DR0) with the verify data bit zero. In like manner, each of the program data bits stored in the data shift register is compared against each of the corresponding verify bits read from a memory location. As illustrated in FIG. 3b, there are ten (10) program data bits (DR0-DR9) stored in the data shift register which are compared against ten (10) verify data bits by XOR gates 380 through 389. The outputs of XOR gates 380 through 389 are coupled to an inverted OR (NOR) gate 390. NOR gate 390 generates a fast verify output which comprises a high logic level when all of the program data bits match all of the corresponding verify data bits. NOR gate 390 generates a fast verify output which comprises a low logic level when one of the program data bits does not match a corresponding one of the verify data bits.
While program verification is performed by compare logic within the 22V10D, the 22V10D architecture suffers from a number of disadvantages. First, the 22V10D architecture is not compatible with the IEEE 1149.1 JTAG) four-pin specification (described below). Second, the only 22V10D instruction (mode) that has multiple functions is the program (DO.sub.-- IT pulse)/fast verify instruction (mode). That is, the 22V10D does not receive an instruction which indicates that the 22V10D should load row, column or program data and then program the received data; rather, there is only one program instruction which programs data into a memory location and verifies the results in response to a program (DO.sub.-- IT) pulse. The 22V10D shifting of the row address, column address, and data registers is always separate and never combined. The user must use the RSEL0 and RSEL1 external signals to control the loading of the various shift registers. Third, the 22V10D codes used for the instructions (modes) are not defined to allow partial shifting to accomplish the changing of one instruction into another instruction. Fourth, the program/fast verify instruction (mode) of the 22V10D only improves the time required to immediately verify a location after programming and then to overprogram, but the speed of the other operations are not improved. Fifth, as described above, the 22V10D combinatorial nature of the compare logic performing a fast verify function does not allow multiple devices to be cascaded together.
Additionally, the 22V10D architecture must compare each and every program data bit against each and every verify data bit. This is a significant disadvantage when considering two types of verification scenarios. In the first scenario, a memory location to be programmed does not comprise the same number of bits as the number of bits in the data shift register. Some memory locations are naturally better suited to be programmed in groups that are less than the size of the data shift register (e.g. programming the one-bit security bit). For example, the data shift register may comprise eight bits and a programmable location may only comprise six bits. Since each and every bit of the data shift register is compared against each and every bit of the verify data, data bits not used for programming in a given programming step would have to be preloaded with predetermined default values. This requires the user to know the default values ahead of time.
The second scenario involves "single-bit programming." Even though the programming of an entire byte of program data is supported by the 22V10D's programming interface, many times only one bit of a byte can be programmed at a time to achieve satisfactory programming. This may be due to the relatively close proximity of the bits of a byte to be programmed within the layout of a particular programmable device. Bits of a byte which must be programmed under the technique of single-bit programming are usually determined during characterization of the device rather than during design and fabrication. In single-bit programming, if n bits of a byte are to be programmed, the same addressed memory location must be programmed and verified with n different data patterns, each data pattern containing the data to program only one bit. The fast verify architecture of the 22V10D does not support single-bit programming. For example, if an eight bit data pattern to be programmed using single-bit programming comprises 00001010 (where a logic one indicates programming a bit in a memory location), the first single-bit programming data pattern to be loaded into the data shift register would comprise 00000010. In the immediately following verify function, the verify data would also comprise 00000010, and the verify function would generate a correct comparison result. The second single-bit programming data pattern to be loaded into the data shift register and programmed into the appropriate memory location would comprise 00001000. The verify data now read from the programmed memory location would now comprise 00001010. This bit pattern would be compared against 00001000 stored in the data shift register. Given that each and every bit of the program data is compared against each and every corresponding bit of the verify data, regardless of whether the program data comprises a logic one or a logic zero, the result of the fast verify would indicate a failure when there was no failure. Therefore, the fast verify architecture as utilized in the 22V10D does not support single-bit programming. Additionally, the 22V10D architecture does not support multi-bit programming. Multi-bit programming is an extension of single-bit programming in that no adjacent bits may be simultaneously programmed.
Therefore, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a PLD, CPLD or other programmable device. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports programming a memory location and immediately verifying the programming. When immediately verifying the programming, the data in the data register remains intact for reprogramming when the memory location does not verify, or for overprogramming when the memory location does verify. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which utilizes a register. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports the cascading of serial test circuits and propagating the fast verify result through the serial test circuits. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which supports single-bit programming or multi-bit programming. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which compares only those bits programmed into a memory location with verify data read from the memory location. Additionally, what is needed is an improved method and apparatus for fast verifying the result of programming memory locations in a CPLD which fills in the bits of a data register with appropriate logic states without the user having to know what default states to load into the data register where there is not a corresponding bit in the memory location, thus excluding those bits from the fast verify comparison.
Another approach to providing a serial programming interface in a device under test is defined in IEEE Std 1149.1-1990 and 1149.1a-1993 entitled IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 1149.1), ISBN 1-55937-350-4, which is commonly referred to as the JTAG (Joint Test Access Group) specification. The JTAG specification defines a test access port (TAP) which is a general purpose port that can provide access to any test support functions built into a component to be tested. The TAP has a minimum of three dedicated input connections: a Test Input Clock (TCK) for clocking in serial test data or instruction information, a Test Mode Select Input (TMS) which is decoded by logic accessing the TAP to control test operations, and Test Data Input (TDI) which provides serial input test data, address information, or instruction information. In addition, the TAP has, at a minimum, one dedicated output: Test Data Output (TDO) which provides for the serial output of data from the TAP. Through the use of the test logic accessed through the TAP, data, address and instruction information may be serially written to and read from a device under test.
FIG. 4a shows a single device under test 400 in which test logic accessed through a TAP may be implemented. Device under test 400 may be a single integrated circuit device or a system on a PCB. Device under test 400 may comprise, for example, a CPLD. Device under test 400 includes a memory 402 comprising programmable memory locations coupled to test circuit 404 via bus 418. Memory 402 receives parallel input data at node 406 and provides parallel output data at node 408. Test circuit 404 receives serial input test data, address data and instruction information from TDI at node 410. Test circuit 404 also receives test input clock TCK at node 412, and test mode select input TMS at node 414. Additionally, test circuit 404 serially outputs TDO at node 416.
FIG. 4b shows a multiple device under test configuration illustrating how components may be cascaded together in a serial fashion in compliance with the JTAG specification. Specifically, device under test 430 is serially coupled to device under test 446 through their respective test circuits 434 and 450. When test circuits 434 and 450 comprise test logic accessed through a TAP, as illustrated in FIG. 4a, test circuits 434 and 450 receive TCK 438 and TMS 440. Test data, address data and instruction information is serially received by test circuit 434 from TDI at node 436 and may be coupled to test circuit 450 via node 442. Test circuit 450 outputs the test data, address data and instruction information at node 452. Test circuits 434 and 450 may be distributed throughout device under test 430 and device under test 446.
FIG. 5 illustrates prior art test logic 500 which operates in accordance with the JTAG specification. Test logic 500 is coupled to memory 528. Memory 528 comprises memory locations in a programmable logic device under test. Test logic 500 comprises controller 503 which includes control logic 502 coupled to decode logic 504. Control logic 502 receives and interprets the signals on TMS at node 518 and TCK at node 520. Control logic 502 and decode logic 504 generate clock and/or control signals as required by test logic 500. A set of registers, including instruction register 506, data register 508, address register 510, boundary scan register 512 and bypass register 514, is configured to receive input signals from decode control logic 504, TCK and TDI.
Through the interaction of control logic 502 and decode logic 504 an instruction is serially loaded into instruction register 506 from TDI. Instructions loaded into instruction register 506 are decoded by decode logic 504 and are used to select a test to be performed and/or register to be accessed. Data register 508 stores program data to be programmed into memory 528 and verify data read from memory 528. Address register 510 stores the address location of the memory location to be accessed in memory 528.
Test logic 500 additionally includes a selector or multiplexer 516 coupled to select signal 526. Selector 516 receives serial data shifted out from data register 508, address register 510, instruction register 506, boundary scan register 512 and bypass register 514. Control logic 502 and decode logic 504 control select signal 526 which selectively enables one of the serial inputs coupled to selector 516 to be serially output at TDO at node 524.
FIG. 6 shows a TAP controller state diagram 600 that is included in the JTAG specification. All test circuitry compliant with the JTAG specification must implement the TAP controller state diagram including states 602 through 632. The TAP controller state diagram would be implemented by controller 503 illustrated in FIG. 5. The TAP controller state diagram is synchronized to the TCK input and is controlled by the TMS input.
FIGS. 7-10 illustrate conventional methods of serially programming a CPLD according to the program flow charts of FIGS. 1 and 2 and using the JTAG compatible test circuit illustrated in FIG. 5. The programming methods illustrated in FIGS. 7-10 are implemented using the TAP controller state diagram illustrated in FIG. 6. Throughout the discussion of FIGS. 7-10, reference will be made to the number of clock cycles that is required to complete a given operation. It will be appreciated that the following discussion generally excludes the calculation of the clock cycles that are required to move from one state to another state in the TAP controller state diagram. These transition clock cycles are generally excluded from the discussion in order to not obscure the general operation of the program flow charts. Additionally, instruction register 506 comprises Z bits, address register 510 comprises Y bits and data register 508 comprises X bits. Therefore, it requires Z clock cycles to shift an instruction into instruction register 506, Y clock cycles to shift address information into address register 510 and X clock cycles to shift program data into data register 508.
FIG. 7 illustrates a conventional method for reading verify data from a memory location in a CPLD using the serial programming interface test circuitry of FIG. 5. The verify data may be compared against an expected result external to the CPLD. The program flow illustrated in FIG. 7 may be used for a number of read steps illustrated in FIG. 1, including: reading or verifying a single memory location such as step 104; reading and verifying multiple locations; and reading and verifying the entire CPLD such as steps 116 and 124. The program flow starts at step 702. At step 704, an instruction is shifted into instruction register 506 which indicates that address information will be shifted into address register (AR) 510. At step 706, the address information is shifted into address register 510. At step 708, an instruction is shifted into instruction register 506 which indicates that verify data is to be read from the memory location addressed by the address information stored in address register 510. At step 710, verify data is captured or read into data register (BR) 508. At step 712, the verify data is shifted out of data register 508 to serial output TDO. Step 714 determines if another memory location within the device is be read. If another memory location is to be read, the program flow returns to step 704. If another memory location is not to be read, the program flow stops at step 716. The program flow illustrated in FIG. 7, requires at least 2Z+Y+X clock cycles to read verify data from one memory location. Reading verify data from subsequent memory locations also requires 2Z+Y+X clock cycles.
FIG. 8 illustrates a conventional method for programming a memory location in a CPLD using the serial programming interface test circuitry of FIG. 5. The program flow illustrated in FIG. 8 may be used for step 120 illustrated in FIG. 1. The program flow starts at step 802. At step 804, an instruction is shifted into instruction register 506 which indicates that address information will be shifted into address register 510. At step 806, address information is shifted into address register 510. At step 808, an instruction is shifted into instruction register 506 which indicates that program data will be shifted into data register 508. At step 810, program data is shifted into data register 508. At step 812, an instruction is shifted into instruction register 506 which indicates that the program data in data register 508 will be programmed into a memory location having the address stored in address register 506. At step 814, the program data is programmed into the memory location. Step 816 determines if another memory location is be to programmed. If another memory location is to be programmed, the program flow returns to step 804. If another memory location is not to be programmed, the program flow stops at step 818. The program flow illustrated in FIG. 8 requires at least 3Z+Y+X clock cycles to program one memory location. Programming subsequent memory locations also requires 3Z+Y+X clock cycles.
FIG. 9 illustrates a conventional method for programming a background pattern into all of the memory locations in a CPLD using the serial programming interface test circuitry of FIG. 5. The program flow illustrated in FIG. 9 may be used for step 112 illustrated in FIG. 1. The program flow starts at step 902. At step 904, an instruction is shifted into instruction register 506 which indicates that program data will be loaded into data register 508. At step 906, program data is shifted into data register 508. At step 908, an instruction is loaded into instruction register 506 which indicates that address information will be loaded into address register 510. At step 910, address information is shifted into address register 510. At step 912, an instruction is shifted into instruction register 506 which indicates that the program data in data register 508 will be programmed into a memory location having the address stored in address register 506. At step 914, the program data is programmed into the memory location. Step 916 determines if another memory location is be to programmed. If another memory location is to be programmed, the program flow returns to step 908. If another memory location is not to be programmed, the program flow stops at step 918. The program flow illustrated in FIG. 9 requires at least 3Z+Y+X clock cycles to program at least one memory location. Programming of subsequent locations requires at least 2Z+Y clock cycles.
FIG. 10 illustrates a conventional method for programming a desired pattern into a CPLD, immediately verifying the programming, and overprogramming the desired pattern. The program flow illustrated in FIG. 10 corresponds to the program flow illustrated in FIG. 2 using the serial programming interface test circuitry of FIG. 5. The program flow starts at step 1002. At step 1004, an instruction is loaded into instruction register 506 indicating that address information will be loaded into address register (AR) 510. At step 1006, address information is shifted into address register 510. At step 1008, C is initialized to zero. At step 1010, the program flow checks to see if C equals the maximum number of programming attempts allowed. In C has reached the maximum number of programming attempts, the programming of the CPLD fails at step 1012. If C has not reached the maximum number of programming attempts allowed, the program flow shifts an instruction into instruction register 506 at step 1014 which indicates that program data will be loaded into data register 508 (BR). At step 1016, program data is shifted into data register 508. At step 1018, an instruction is shifted into instruction register 506 which indicates that program data in data register 508 will be programmed into a memory location having the address stored in address register 510. At step 1020, the program data is programmed into the memory location.
At steps 1022 through 1028, the programming of the memory location is immediately verified to determine if another attempt to program the same memory location is required. At step 1022, an instruction is loaded into instruction register 506 which indicates that verify data will be read from the programmed memory location. At step 1024, the verify data is read or captured into data register 508. At step 1026, the verify data is shifted out of data register 508 to serial output TDO. At step 1028, the verify data is externally compared against the programmed data. If the verify data does not match the program data, the program flow increments C at step 1029 and returns to step 1010. If the verify data matches the program data, the program flow overprograms the program data into the same memory location at steps 1030 through 1036. At step 1030, an instruction is shifted into instruction register 506 which indicates that the program data will be reloaded into data register 508. At step 1032, the program data is reshifted into data register 508. At step 1034, an instruction is shifted into instruction register 506 which indicates that the reloaded program data will be overprogrammed into the memory location. At step 1036, the program data is overprogrammed into the memory location. At step 1038, the program flow determines if another memory location needs to be programmed in accordance with the desired program pattern. If another memory location is to be programmed, the program flow returns to step 1004. If no other memory locations are to be programmed, the program flow stops at step 1040. The program flow illustrated in FIG. 10 requires at least 6Z+Y+3X clock cycles to program, verify and overprogram one memory location.
An alternative program flow based on FIG. 10 shifts the original program data into data register 508 at the same time the captured verify data is being shifted out of data register 508 at step 1026. This alternative obviates the need for steps 1030 and 1032 reducing the number of clock cycles required to program, verify and overprogram one memory location to at least 5Z+Y+2X clock cycles. Additionally, the number of cycles required to reprogram a memory location after the first memory location did not verify requires at least 2Z+X clck cycles (steps 1014 and 1016 are then not required for reprogramming).
The programming methods illustrated in FIGS. 7-10 require a significant number of clock cycles to program a memory location in a device under test, to verify the programming, and to reprogram or overprogram the memory location. The more clock cycles that are required to test a device, the lower the testing throughput and the greater the likelihood that a false programming error will be introduced due to system noise.
Therefore, a need exists for a method of programming and testing a device which reduces the number of method steps, instructions and clock cycles over the conventional methods illustrated in FIGS. 7-10. Additionally, a need exists for implementing such a method using test circuitry which is compatible with the JTAG specification. Additionally, a need exists for a method of programming and testing a device which uses multi-purpose instructions which define both programming and shifting operations in order to reduce the number of required method steps, instructions and clock cycles. Additionally a need exists for instruction codes which allow partial shifting to accomplish the changing of one instruction into another instruction in a number of clock cycles which is less than the number of clock cycles required to completely load every bit of an instruction register.